Computer systems currently employ different kinds of communication links between various components within a computer system. Some of these communication links are, or have been, multi-drop, parallel busses. However, with increasing processing power and higher capacity data links, it is expected that serial, point-to-point busses will be employed in place of some multi-drop, parallel busses. One such multi-drop bus, the PCI (Peripheral component Interconnect) bus, is expected to be replaced with the PCI Express bus. (PCI and PCI Express are registered trademarks belonging to the PCI SIG Corporation. See www.pci-sig.com.)
The physical layer specified by the PCI Express Architecture is a point-to-point serial data bus employing differential signaling in each direction. A lane in the physical layer comprises two low-voltage differentially driven communication links, or channels. This is illustrated in FIG. 1, where device A comprises a differential transmitter Tx to transmit a differential signal to device B, and comprises a receiver Rx to receive a differential signal from device B. Device B also comprises a differential transmitter Tx and a differential receiver Rx. The resistors in FIG. 1 indicate termination resistors.
The data transmitted in the PCI Express link is in the form of packets, where 8 b/10 b encoding is employed so that 8 information bits are encoded into 10 channel bits to equalize the number of 1's and 0's sent. The encoded signal contains an embedded clock. It is expected that a single lane in the PCI Express Architecture will support a data rate of 2.5 Gbps (Giga bits per second). Higher data rates between devices may be realized by employing more than one physical lane.
Recovering the transmitted information from a high speed serial link is not necessarily a straightforward task, particularly in those cases in which the channel capacity of the transmission medium may be limited. Channel capacity may be limited if the bandwidth of the transmission channel, such as for example a transmission line comprising copper wires, is below that of the transmitted data rate. Such bandlimited channels may result in intersymbol interference. In such cases, channel equalization is a method to mitigate the effects of intersymbol interference.
In many applications, recovering data at the receiving end involves sampling the received data signal, establishing common mode levels to optimal bias levels, canceling offset errors in comparators, equalizing data-dependent jitter, and amplifying the filtered output to full CMOS (Complementary Metal Oxide Semiconductor) voltage levels. Performing some or all of these signal processing operations with dedicated discrete circuit blocks may not be an ideal solution because of power consumption and required die area, and because of the noise and distortion that may be introduced.
It is desirable to provide a circuit to perform some or all of these functions that is relatively small and consumes relatively little power.